1. Technical Field of the Invention
The present invention relates to a Network-on Chip (NoC) for use in connecting different subsystems of a System-on-Chip (SoC) using a rotation principle with an extension of a basic ring architecture.
2. Description of Related Art
A Network-on-Chip (NoC) is a System-on-Chip (SoC) component used to connect different sub-systems of the SoC. For example, an NoC can be used to connect a set of embedded processors and other processing components with a set of memories and Input/Output (I/O). A bus can be considered as a low-cost, low-bandwidth NoC, while a full cross-bar can be considered a high-cost, high-bandwidth NoC.
A 2D Torus architecture is disclosed in W. J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks”, Design Automation Conference (DAC), Jun. 18-22, 2001, Las Vegas, Nev., USA, pp. 684-689. The architecture is a variant of a 2D Mesh topology, and uses a switch at each resource, where the switches are connected to form a ring topology in each direction. Each switch is composed of a four output buffer, one output for each direction, where traffic can be routed in any direction, without following a particular routing scheme.
As will be described in more detail herein, the present invention comprises a Hyper-Ring-on-Chip (HyRoC) architecture that is based on generally the same topology as the 2D Torus. However, one difference between the two architectures is that the switching at each hop in the HyRoC Architecture is configured as add-drop multiplexing in each direction. This results in a different scheduling scheme than is present with the 2D Torus implementation of the prior art. When a message is being transferred in one direction (ring) with the HyRoC Architecture, it will not be blocked at a hop before reaching its destination hop relative to that current ring. Furthermore, the use of multiple parallel channels is proposed in the HyRoC Architecture of the present invention to minimize internal blocking (internal blocking occurs when traffic for a given source-destination path on a ring is blocking traffic for an independent source-destination path). The basic principle of the single ring with multiple parallel channels is derived from the rotator-switch architecture disclosed by M. E. Beshai and E. A. Munter, “Rotating-Access ATM-STM Packet Switch, U.S. Pat. No. 5,168,492. This architecture target telecommunication application based on multi-chip implementation, and is using a complex scheduler to maximize resource utilization, resulting in a relatively large routing latency. In our case, for the HyRoC architecture, we target a simpler on-chip implementation using a simpler scheduler to minimize the routing latency. Furthermore, we proposed a multi-dimensional ring implementation, in particular, a 2D extension of bidirectional rings.
A prior art ClearConnect architecture (ClearSpeed Technology ClearConnect Bus, www.clearspeed.com) discloses a basic multiplexer block which can be connected to form a chain topology, but not a ring topology. Although bidirectional chains are supported, there is no support for multiple channels, nor is there support for multiple dimensions, such as a 2D dimension. As will be described in more detail herein, the scheduling and routing mechanism of the HyRoC Architecture is very different from the ClearConnect Bus as well.